The invention relates generally to fabrication of a semiconductor device and, more particularly, to a method of fabricating a bitline in a semiconductor device.
The critical dimension of a bitline stack has been sharply reduced in development of semiconductor devices as such devices have become more highly integrated. Since spaces disposed between the bitline stacks have also been reduced in size due to reduction in the critical dimension of the bitline stack, it is difficult to gap-fill the bitline stack with previously-employed gap-filling methods. In one method of gap-filing the bitline stack, a high density plasma (HDP) process is employed. However, with the reduction in the critical dimension of the bitline stack, there occurs a bending phenomenon wherein a bit line stack is inclined in a direction when the bitline stack is gap-filled using the high density plasma process. This bending phenomenon is caused by an abnormal deposition of an oxide layer on both sides of the bitline stack upon deposition using the high density plasma process or by damage due to plasma in the high density plasma process.
Due to this limitation in the process, most bitline stacks currently employ a spin on dielectric (SOD). The spin on dielectric is formed by spin coating of a liquid compound, substitution with an oxide layer using a high temperature curing process, and gap-filling. The spin on dielectric has been developed for an isolation material, but is now being developed, in fine devices, for use in a process requiring gap-filling such as in a gate stack or bitline stack. However, as device sizes become smaller, the spin on dielectric also has a problem in that a surface of the spin on dielectric is cracked due to variation in stress and variation in volume of the spin on dielectric itself during the curing process for the spin on dielectric or a subsequent thermal process.
To overcome the aforementioned problems, there has been proposed a method of gap-filling a bitline stack using a dual layer of a spin on dielectric employed in an isolation process and a high density plasma oxide layer. The proposed method is a process of gap-filling a bitline stack by coating the bitline stack with a spin on dielectric, implementing a curing process, planarizing the gap-filled spin on dielectric, etching a predetermined height, and then additionally gap-filling bitline stack using a high density plasma oxide layer. This dual layer of the spin on dielectric and the high density plasma oxide layer has an excellent gap-filling property and can prevent the bending defect, but requires additional process steps and creates an additional problem caused by the lower placed spin on dielectric.
Particularly, the spin on dielectric remaining in a peripheral region causes a gap-filling defect of a metal wiring line and a lifting defect of the spin on dielectric. The gap-filling defect of the metal wiring line is generated when a barrier metal layer of the metal line contact is deposited non-uniformly due to outgassing from the spin on dielectric when the metal line comes in contact with the spin on dielectric present at a side face of the metal line due to misalignment upon formation of a metal line contact mask. Also, in the lifting defect of the spin on dielectric, a large sized plate-like defect is generated as, when the spin on dielectric is used for each of an isolation layer, a first interlayer insulation layer, and a second interlayer insulation layer, the spin on dielectric layers are stacked from a lower side and the spin on dielectric is separated in a subsequent thermal process.
In another example, there has been developed a method of implementing deposition-etch-deposition (DED) and deposition-wet etch-deposition (DWD) processes when gap-filling between bitline stacks with a single layer of a high density plasma oxide layer. This method can improve the problems associated with gap-filling defects and plate-like defects, but is limited due to the lack of a gap-fill margin and a bending margin.
As described above, gap-filling between the bitline stacks using the single layer of the high density plasma layer, the single layer of the spin on dielectric, or the dual layer of the high density plasma oxide layer and the spin on dielectric is characterized by various problems in process reliability. Therefore, there is required a method that does not cause a defect and ensure process reliability while completely gap-filling between the bitline stacks.